TMPR4955AF datasheet(88/168 Pages) TOSHIBA

88 / 168 page

Chapter 6 TX4955A System Interface

6-16

2. Reissue write

When in the reissue write mode, the WrRdy* signal is asserted for 1 cycle 2 cycles

before the address cycle, and the write operation is reissued when the WrRdy*

signal is asserted during the address cycle. Figure 6.2.15 illustrates the reissue

write protocol.

•

By asserting (Low) the WrRdy* signal in the first and third cycles,

Addr0/Data0 issues a write operation in the third or fourth cycle.

•

By deasserting (High) the WrRdy* signal in the fifth cycle, Addr1/Data1 does

not issue a write operation in the fifth and sixth cycles.

•

By asserting (Low) the WrRdy* signal again in the eighth and tenth cycles,

Addr1/Data issues a write operation in the tenth and eleventh cycles.

Figure 6.2.15 Reissue Write Protocol

3. Pipeline write

Similar to when in the R4000 compatible write mode, the pipeline write protocol

issues a write operation if the WrRdy* signal is asserted for 1 cycle 2 cycles before

the write operation is issued. However, the 2 cycles of dummy data after the write

operation are deleted. The external agent must be able to accept one write

operation or more after WrRdy* is deasserted. Figure 6.2.16 illustrates this

protocol.

•

Third, fourth cycle Addr0/Data0 is issued by asserting (Low) the WrRdy*

signal in the first cycle.

•

Fifth, sixth cycle Addr1/Data1 is issued by asserting (Low) the WrRdy* signal

in the third cycle.

•

Addr2 is not issued in the seventh cycle when the WrRdy* signal is deasserted

(High) in the fifth cycle. Addr2/Data2 is issued in the tenth, eleventh cycle by

asserting the WrRdy* signal again in the eighth cycle.

Figure 6.2.16 Pipeline Write Protocol

345

Cycle

Master Clock

SysAD Bus

WrRdy*

SysCmd Bus

Addr0

Issue

Data0

Addr1

Data1

Data 1

Write

NEOD

Write

NEOD

Issue

Addr1

Write

345

Cycle

Master Clock

SysAD Bus

WrRdy*

SysCmd Bus

Addr0

Issue

Data0

Addr1

Data1

Data 1

Write

NEOD

Write

NEOD

Issue

Addr2

Write

Issue

TMPR4955AF датащи(PDF) 88 Page - Toshiba Semiconductor

TMPR4955AF датащи(HTML) 88 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL