TMPR4955AF datasheet(10/168 Pages) TOSHIBA

10 / 168 page

TMPR4955A

7.3.2

Bypass Register ...................................................................................................................... 7-4

7.3.3

Boundary-Scan Register ........................................................................................................ 7-5

7.3.4

Device Identification Register ............................................................................................... 7-5

7.3.5

Test Access Port (TAP) ........................................................................................................... 7-6

7.3.6

TAP Controller........................................................................................................................ 7-6

7.3.7

Controller Reset ..................................................................................................................... 7-6

7.3.8

TAP Controller........................................................................................................................ 7-7

7.4

Instructions for JTAG ..................................................................................................................7-11

7.4.1

The EXTEST Instruction......................................................................................................7-11

7.4.2

The SAMPLE/PRELOAD Instruction................................................................................. 7-12

7.4.3

The BYPASS Instruction .....................................................................................................7-13

7.4.4

The IDCODE Instruction.....................................................................................................7-13

7.5

Note .............................................................................................................................................. 7-14

Chapter 8. TX4955A Processor Interrupts .............................................................................................. 8-1

8.1

Nonmaskable Interrupt ................................................................................................................ 8-1

8.2

External Interrupts ....................................................................................................................... 8-1

8.3

Software Interrupt ........................................................................................................................ 8-1

8.4

Timer Interrupt ............................................................................................................................. 8-2

8.5

Asserting Interrupts...................................................................................................................... 8-3

Chapter 9. Debug Support Unit ............................................................................................................... 9-1

9.1

Features ......................................................................................................................................... 9-1

9.2

EJTAG interface ............................................................................................................................ 9-1

9.3

JTAG Interface .............................................................................................................................. 9-2

9.4

Processor Access Overview ........................................................................................................... 9-2

9.5

Instruction ..................................................................................................................................... 9-2

9.6

Debug Unit..................................................................................................................................... 9-3

9.6.1

Extended Instructions............................................................................................................ 9-3

9.6.2

Extended Debug Registers in CP0 ........................................................................................ 9-3

9.7

Register Map.................................................................................................................................. 9-3

9.8

Processor Bus Break Function ..................................................................................................... 9-3

9.9

Debug Exception............................................................................................................................ 9-4

9.9.1

Debug Single Step (DSS) ....................................................................................................... 9-4

9.9.2

Debug Breakpoint exception (Dbp) ....................................................................................... 9-4

9.9.3

JTAG Break Exception .......................................................................................................... 9-4

9.9.4

Debug Exception Handling.................................................................................................... 9-4

9.9.5

Branching to debug handler .................................................................................................. 9-4

9.9.6

Exception handling when in Debug Mode (DM bit is set) ................................................... 9-4

9.10 Real Time PC TRACE Output ...................................................................................................... 9-4

Chapter 10. Electrical Characteristics .................................................................................................... 10-1

10.1 Electrical Characteristics of TMPR4955AF............................................................................... 10-1

10.1.1 Absolute Maximum Ratings ................................................................................................ 10-1

10.1.2 Recommended Operating Conditions.................................................................................. 10-1

10.1.3 DC Characteristics ............................................................................................................... 10-2

10.1.4 AC Characteristics ............................................................................................................... 10-2

10.1.4.1

Clock Timing................................................................................................................. 10-2

10.1.4.2

System Interface .......................................................................................................... 10-2

10.1.5 Timing Diagrams.................................................................................................................. 10-3

10.1.5.1

Clock Timing................................................................................................................. 10-3

10.1.5.2

PClock to SClock DIVISOR of 2 .................................................................................. 10-3

10.1.5.3

System Interface Timing ............................................................................................. 10-4

10.1.5.4

Cold Reset Timing ........................................................................................................ 10-4

10.1.5.5

Warm Reset Timing...................................................................................................... 10-4

Chapter 11. Package Dimension ...............................................................................................................11-1

A. PLL Passive Components .....................................................................................................................A-1

B. Movement parameter setting of a processor........................................................................................B-1

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