TMPR4955AF datasheet(84/168 Pages) TOSHIBA

84 / 168 page

Chapter 6 TX4955A System Interface

6-12

6.2.8

Processor Request and External Request Protocol

This section explains the bus arbitration protocol for both processor requests and

external requests on a cycle-by-cycle basis. Table 6.2.3 below describes the abbreviations

used in the following timing diagram of the bus.

Table 6.2.3 System Interface Request

Range

Abbreviation

Meaning

Total

Unsd

Unused

Addr

Physical address

SysAD bus

Data<n>

Data number n of the data block

Cmd

Undefined system interface command

Read

Processor or external read request command

Write

Processor or external write request command

SINull

External null request command that releases the

system interface

NData

Non-coherent data identifier for datum other than

the final datum

SysCmd bus

NEOD

Non-coherent data identifier for the final datum

6.2.8.1

Processor request protocol

Processor request protocol is as follows.

•

Read

•

Write

•

Null write

6.2.8.2

Processor read request protocol

The processor read request protocol is as described in the following sequence. The

next step numbers correspond to the numbers in Figure 6.2.12.

1. RdRdy* is asserted to Low by the external agent. This means that the external

agent is ready to accept read requests.

2. When the system interface is in the master state, the read command is

transmitted to the SysCmd bus, then the processor read request is issued by

transmitting the read address to the SysAD bus.

3. At the same time, the processor asserts the ValidOut* signal for one cycle. This

means that valid data are being transmitted to the SysCmd bus and SysAD bus.

4. The processor goes into the slave state by itself either at the issue cycle of a read

request or after the Release* signal is asserted for one cycle and the issue cycle of

the read request is complete.

Note: The external agent must not assert the ExtRqst* signal as a means of

returning a read response. It must however wait to shift to the slave state on its

own. If an external request other than a read response is issued, ExtRqst* can be

asserted either before the read response or in the process of the read response.

5. The SysCmd bus and SysAD bus are released from the processor one cycle after

the Release* signal is asserted.

6. The SysCmd bus and SysAD bus are driven by the external agent within two

cycles after the Release* signal is asserted.

When shifting to the slave state (from Cycle 5 in Figure 6.2.12), the external agent

can return the requested data as a read response. Notification of an error in the

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