TMPR4955AF datasheet(93/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-21

6.2.8.10 External write request protocol

The same protocol as the processor single word write protocol is used for external

write requests, except when the ValidIn* signal is asserted instead of the ValidOut*

signal.

Figure 6.2.21 illustrates the timing of the external write request, which consists of

the following steps.

1. The external agent requests use of the system interface by asserting ExtRqst*.

2. The processor asserts Release*, then the system interface is released from the

processor and goes into the slave state.

3. The external agent sends a write command to the SysCmd bus, and sends a write

address to the SysAD bus while asserting ValidIn*.

4. The external agent sends data identifiers to the SysCmd bus, and sends data to

the SysAD bus while asserting ValidIn*.

5. Data identifiers for this data cycle must contain an indication of a coherent or

non-coherent final data cycle.

6. After a data cycle is issued, the write request is complete, the external agent sets

the SysCmd and SysAD busses to tri-state, then the system interface returns to

the master state. Timing of the SysADC bus and SysCmdP bus are each the same

as the SysAD bus and SysCmd bus, respectively.

External write requests can write only 1 word of data to the processor. Operation of

processors that have specified data elements other than a single word of data by an

external write request is not defined.

Figure 6.2.21 External Write Request when System Interface Starts in the Master State

345

Cycle

Master Clock

SysAD Bus

ValidOut*

Validln*

SysCmd Bus

ExtRqst*

Release*

Master

Addr

Data0

Slave

Master

Write

NEOD

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