TMPR4955AF datasheet(76/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-4

•

Complete issuing of processor requests before external requests are received.

•

Release the system interface and go into the slave mode without completing

issuance of the processor requests.

In the latter of the above situations, the TX4955A issues processor requests after

external requests are complete. Rules relating to issuing are also provided to processor

requests.

6.2.4

Handshake signal

The processor uses the eight control signals explained below to manage the flow of

requests.

•

RdRdy* and WrRdy* are used by the external agent to indicate that it is ready to

accept a new read or write transaction.

•

ExtRqst* and Release* are used to transfer SysAD bus and SysCmd bus control.

ExtRqst* is used by the external agent to indicate the necessity of controlling the

interface. Release* is asserted by the processor when transferring the system

interface access privileges.

•

The TX4955A processor uses ValidOut* and the external agent ValidIn* signals to

indicate the valid command/data on the SysCmd/SysAD bus.

6.2.5

System Interface Protocol of R5000 type

Figure 6.2.4 illustrates the system interface that operates between registers. In other

words, processor output is directly transferred from the output register and changes and

the Master Clock rising edge.

Processor input is directly transferred to the input register and the input register latches

these input signals at the rising edge of the Master Clock. In this way, it becomes possible

for the system interface to operate at the fastest clock frequency.

Figure 6.2.4 Operation of the System Interface Between Registers

Master Clock

TX4955A

Output data

Input data

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