TMPR4955AF datasheet(71/168 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-11

5.10.1

Cache Write Policy

The TX4955A processor manages its data cache by using a write-back and a write-through

policy. A write-back stores write data into the cache, instead of writing it directly to

memory. Some time later this data is independently written into memory. In the TX4955A

implementation, a modified cache line is not written back to memory until the cache line is

to be replaced either in the course of satisfying a cache miss, or during the execution of a

write-back CACHE instruction.

When the processor writes a cache line back to memory, it does not ordinarily retain a

copy of the cache line, and the state of the cache line is changed to invalid.

A write-through is written simultaneously to cache and memory.

5.10.2

Data Cache Line Replacement

Since the data cache uses a write-back and a write-through methodology, a cache line

load is issued to main memory on a load or store miss, as described below. After the data

from memory is written to the data cache, the pipeline resumes execution.

TX4955A does not support “Critical Data Word First”. Always it transfer the data of first

address.

Rules for replacement on data load and data store misses are given below.

• Data Load Miss

Data Load Miss

If the missed line is not dirty, it is replaced with the requested line.

If the missed line is dirty, it is moved to the write buffer. The requested line replaces

the missed line, and the data in the write buffer is written to memory.

• Data Store Miss

Data Store Miss

If the missed line is not dirty, the requested line is merged with the store data and

written to memory.

If the missed line is dirty, it is moved to the write buffer. The requested line is

merged with the store data and written to cache, and data in the write buffer is

written to memory.

The data cache miss penalties, in number of SClock cycles, are given in Table

5.10.2.

Table 5.10.2 Data Cache Refill Penalty Cycle Count

Number of

PClock Cycles

Action

Stall the DC stage.

Transfer address to the write buffer and wait for the pipeline start signal

∼ 2

Transfer address to the internal SysAD bus on the SClock.

Transfer to the external SysAD bus.

Time needed to access memory, measured in PClock cycles.

Transfer the cache line form memory to the SysAD bus.

Transfer the cache line from the external bus to the internal bus.

Restart the DC stage.

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