TMPR4955AF datasheet(83/168 Pages) TOSHIBA

83 / 168 page

Chapter 6 TX4955A System Interface

6-11

•

If the coherency properties are non-coherent write back or non-coherent write

through (write allocate), then a non-coherent block read request is issued.

•

If the coherency properties are non-coherent write through (non-write

allocate), then a non-block write request is issued. Table 6.2.2 indicates the

measures taken when there is a store miss to the primary cache.

Table 6.2.2 Store Miss to Primary Cache

State of the replaced data cache line

Page Properties

Dirty (W = 0)/Invalid

Dirty (W = 1)

Non-coherent write back or non-coherent write through

(write allocate)

NCR

NCR/W

Non-coherent write through (non-write allocate)

NCW

NCR: Processor non-coherent, block read request

NCR/W: Processor non-coherent, block write requests continue after the block read request

NCW: Processor non-coherent write request

6.2.7.3

Store hits

Operation in the system interface is determined by whether a line is write back or

write through. When in the primary cache mode, all lines set to write back are set to

the dirty exclusion state (W = 1). In other words, burst transactions do not occur even

if a store hit occurs. Lines set to write through generate processor write requests for

store data.

6.2.7.4

Uncached load or store

When performing uncached load operations, the processor issues non-coherent read

requests for double words, partial double words, words, or partial words. Also, when

performing uncached store operations, the processor issues write requests for double

words, partial double words, words, or partial words.

The TX4955A judges that there is valid parity and data in the entire 32-bit SysAD

bus even for data requests of less than words. Even if there was a partial word request

for example, all parity must be correctly returned for all 32 bits. If not, then parity

check must be disabled.

All write transactions by the TX4955A are buffered in the 4-stage write buffer of the

system interface. If there are entries in the write buffer when a block request is

required, the write buffer is flushed before a read request is generated (for cache

misses or read transactions to uncached areas). Data cache misses or uncached data

load transactions flush the write buffer.

6.2.7.5

Cache instruction operation

Various operations are made available to the Cache instruction in order to maintain

the primary cache status and contents. When Cache instruction operations are in

progress, write requests or invalidate requests can be issued from the processor.

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