TMPR4955AF datasheet(92/168 Pages) TOSHIBA

номер детали	TMPR4955AF

подробное описание детали	64-Bit TX System RISC TX49 Family

PDF	168 Pages

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производитель	TOSHIBA [Toshiba Semiconductor]

домашняя страница	http://www.semicon.toshiba.co.jp/eng

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Chapter 6 TX4955A System Interface

6-20

6.2.8.9

External null request protocol

The processor only supports one external null request. The system interface release

external null request returns the system interface from the slave state to the master

state. This request does not affect any other processors.

The only processing the external null request does is to have the processor return

the system interface to the master state.

Figure 6.2.20 illustrates the timing of the external null request, which consists of

the following steps.

1. The external agent drives the system interface, sends the external null request

command to the SysCmd bus, then asserts the ValidIn* signal for 1 cycle.

2. The SysAD bus is not available during the external null request address cycle

(there are no valid data in the bus).

3. The null request ends when the address cycle is issued.

In the case of a system interface release null request, the external agent releases the

SysCmd bus and SysAD bus so the system interface can return to the master state.

Figure 6.2.20 System Interface Release External Null Request

345

Cycle

Master Clock

SysAD Bus

ValidOut*

Validln*

SysCmd Bus

Extqst*

Release*

Slave

Unsd

SINull

Master

TMPR4955AF датащи(PDF) 92 Page - Toshiba Semiconductor