TMPR4955AF datasheet(54/168 Pages) TOSHIBA

54 / 168 page

Chapter 3 Initialization Interface

3-4

3.3

TX4955A

The TX4955A processor supports several user-selectable modes. All modes except DivMode

DivMode

ratios are set/reset by writing to the

Status and Config registers.

3.3.1

Power Modes (Doze/Halt Mode)

The TX4955A supports three power modes: normal operation, Doze, and Halt. This

section describes these three modes. In TX4955A, there is a terminal showing that the

status is Halt mode or Doze mode state.

Figure 3.3.1 show the status shifts in the operation mode.

Figure 3.3.1 Status Shift Among Normal Operation Mode and Low Power Consumption Modes

•

Normal Operation Mode

Normally the TX4955A processor clock (PClock

PClock

PClock) operates at a multiple of the

MasterClock

MasterClock speed (as designated by the DivMode

DivMode

DivMode setting). The System Interface

Clock (SClock

SClock

SClock) operates at the same frequency as MasterClock

MasterClock

MasterClock.

•

Doze Mode

The user can specify Doze mode by setting the Halt bit in the Config Register to 1

after excuting a Wait instruction. Consumption power is bigger than later Halt mode so

that a circuit maintaining pipeline status works in Doze mode.

To recover from Doze mode, assert one of the following signal:

Int[5:0]*, NMI*, Reset*, or ColdReset*.

When recovering from Doze mode by asserting a non-enabled Int[5:0]* signal, the

value of the Int Mask field in the Status Register is not affected.

When recovering from Doze mode via the ColdReset* signal, NMI* signal, or an

enabled Int[5:0]* signal, the top instruction of the exception handler corresponding to

the signal is executed. On execution of the top instruction, the EPC points to

instruction following the Wait instruction. When recovering via a non-enabled Int[5:0]*

signal, the processor resumes execution from the instruction following the instruction

used to change to Doze mode.

•

Halt Mode

The user can change to Halt mode by setting the Halt bit in the Config resister to 0

after excuting a Wait instruction.

In Halt mode, operations are suspended with the pipeline state retained.

Even requests for bus mastership are ignored. When an instruction that clears the

HALT bit = 0 and WAIT inst.

HALT bit = 1 and WAIT inst.

Halt Mode

Doze Mode

Normal Operation

Mode

Interrupt or Reset

TMPR4955AF датащи(PDF) 54 Page - Toshiba Semiconductor

TMPR4955AF датащи(HTML) 54 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL