TMPR4955AF datasheet(137/168 Pages) TOSHIBA

137 / 168 page

Chapter 7 JTAG Interface

7-3

7.3

JTAG Controller and Registers

The processor contains the following JTAG controller and registers:

•

Instruction register

•

Boundary-scan register

•

Bypass register

•

ID Code register

•

Test Access Port (TAP) controller

The processor executes the standard JTAG EXTEST operation associated with External Test

functionality testing.

The basic operation of JTAG is for the TAP controller state machine to monitor the JTMS

input signal. When it occurs, the TAP controller determines the test functionality to be

implemented. This includes either loading the JTAG instruction register (IR), or beginning a

serial data scan through a data register (DR), listed in Table 8-1. As the data is scanned in, the

state of the JTMS pin signals each new data word, and indicates the end of the data stream.

The data register to be selected is determined by the contents of the

Instruction register.

7.3.1

Instruction Register

The JTAG

Instruction register includes eight shift register-based cells; this register is

used to select the test to be performed and/or the test data register to be accessed. As listed

in Table 7.3.1, this encoding selects either the

Boundary-scan register or the Bypass

Table 7.3.1 JTAG Instruction Register Bit Encoding

Instruction Code

(MSB

→ LSB)

Instruction

Selected Data Register

00000000

EXTEST

Boundary Scan Register

00000001

SAMPLE/PRELOAD

Boundary Scan Register

00000010

Reserved

00000011

IDCODE

Device Identification register

00000100 ~ 01111111

Reserved

10000000 ~ 11111110

Debug Support Unit

Please refer DSU section

11111111

BYPASS

Bypass register

Figure 7.3.1 shows the format of the

Instruction register

MSB

LSB

Figure 7.3.1 Instruction Register

The instruction code is shifted out to the Instruction register from the LSB.

Figure 7.3.2 Instruction Register Shift Direction

LSB

JTDO

JTDI

MSB

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