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TMPR4955AF датащи(PDF) 87 Page - Toshiba Semiconductor

номер детали TMPR4955AF
подробное описание детали  64-Bit TX System RISC TX49 Family
PDF  168 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
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TMPR4955AF датащи(HTML) 87 Page - Toshiba Semiconductor

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Chapter 6 TX4955A System Interface
6-15
6.2.8.4
Processor single write requests
There are three processor single write requests as follow below.
With later G2SConfig-Regster, these modes are selected.
1. R4000 compatible write
2. Reissue write
3. Pipeline write
Table 6.2.4 Data Transfer Rate, Data Pattern and Setting at single write requests
Maximum Data Transfer Rate
Data Pattern
Setting Bit(2:1)
Write mode
1 double word/3 Master Clock cycle
Dxx
00
R4000 compatible
Reserved
Reserved
01
Reserved
1 double word/1 Master Clock cycles
D
10
Pipeline write
1 double word/1 Master Clock cycles
D
11
Reissue write
Note: The setting Bit(2:1) is bit(2:1) of the G2Sconfig register (0xF FF10 0000).
Bit(2:1) is set to “00” when initialized.
1. R4000 compatible write
When in the R4000 compatible write mode, 4 cycles are required for single write
operation. After the address is asserted for 1 cycle, it is followed by 2 cycles of
dummy data. Figure 6.2.14 illustrates its basic operation.
In the case of the TX4955A, the WrRdy* signal must be asserted for 1 cycle 2
cycles before the write operation is issued. When in the R4000 compatible signal
write mode, the external agent receives the write data then immediately asserts
WrRdy*, making it possible to stop write operation that continues after 4 cycles.
The 2 cycles of dummy data that follow these write data give the external agent
time to stop the next write operation.
Figure 6.2.14 R4000 Compatible Write
1
2
345
6
Cycle
Master Clock
SysAD Bus
ValidOut*
Validln*
78
9
10
11
12
SysCmd Bus
Addr
RdRdy*
WrRdy*
Release*
Data 0
Addr
Data 1
Addr
Write
NEOD
Write
NEOD
Write



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