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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMPR4955AF датащи(PDF) 62 Page - Toshiba Semiconductor |
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TMPR4955AF датащи(HTML) 62 Page - Toshiba Semiconductor |
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62 / 168 page  Chapter 5 Cache Organization 5-2 5.2 Cache Organization This section describes the organization of the on-chip data and instruction caches. Figure 5.2.1 provides a block diagram of the TX4955A cache and memory model. Main Memory Cache Controller I-cache: Instruction cache D-cache: data cache D-cache I-cache Caches TX4955A Figure 5.2.1 TX4955A Cache Support 5.2.1 Cache Sizes The TX4955A instruction cache is 32 Kbytes; the data cache is 32 Kbytes. 5.2.2 Cache Line Lengths A cache line is the smallest unit of information that can be fetched from main memory for the cache, and that is represented by a single tag.(Note) The line size for the instruction cache is 8 words (32 bytes) and the line size for the data cache is 8 words (32 bytes). Note: Cache tags are described in the following sections. 5.2.3 Organization of the Instruction Cache (I-Cache) Each line of I-cache data (although it is actually an instruction, it is referred to as data to distinguish it from its tag) has an associated 24-bit tag. The TX4955A processor I-cache has the following characteristics: • Cache size: 32 KB • Four-way set associative • FIFO replacement • Indexed with a virtual address • Checked with a physical tag • Block (line) size: 8 words (32 bytes) • Burst refill size: 8 words (32 bytes) • Lockable on a per-line basis (way1 ∼ way3) • All valid bits, lock and FIFO bits are cleared by a Reset exception |
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