TMPR4955AF datasheet(51/168 Pages) TOSHIBA

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Chapter 3 Initialization Interface

3-1

Chapter 3.

Initialization Interface

This chapter describes the TX4955A Initialization interface, and the processor modes. This

includes the reset signal description and types, and initialization sequence, with signals and

timing dependencies, and the user-selectable TX4955A processor modes.

Signal names are listed in bold letters—for instance the signal MasterClock

MasterClock

MasterClock indicates the

processor clock. Low-active signals are indicated by a trailing asterisk, such as ColdReset

ColdReset

ColdReset*, the

power-on/cold reset signal.

3.1

Functional Overview

The TX4955A processor has the following two types of resets; they use the ColdReset

ColdReset

ColdReset*

and Reset

Reset

Reset* input signals.

•

Cold Reset

Cold Reset is asserted after the power supply is stable and then restarts all clocks. A

cold reset completely reinitializes the internal state machine of the processor without

saving any state information.

•

Warm Reset

Warm Reset restarts processor, but does not affect clocks. A warm reset preserves the

processor internal state.

After reset, the processor is bus master and drives the

SysAD bus.

For reset vector address, use Oxbfc0 0000.

In the TX49/H2 processor core, the reset vector is located in address space without caching.

Therefore, the cache and TLB need not be initialized at reset processing.

3.1.1

System Coordination

Care must be taken to coordinate system reset with other system elements. In general,

bus errors immediately before, during, or after a reset may result in unpredicted behavior.

Also, a small amount of processor state is guaranteed as stable after a reset of the TX4955A

processor, so extreme care must be taken to correctly initialize the processor through

software.

The operation of each type of reset is described in sections that follow. Refer to Figure

3.2.1 and Figure 3.2.2 later in this chapter for timing diagrams of the cold and warm resets.

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