MPC821 datasheet(152/242 Pages) NXP

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Support Information

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

if (END_OF_FLASH_READ & DSyncHardReset~.fb) then

HOLD_OFF_CONSIDERED

else

NO_HOLD_OFF;

state HOLD_OFF_CONSIDERED:

if (END_OF_OTHER_CYCLE # !DSyncHardReset~.fb) then

NO_HOLD_OFF

else

HOLD_OFF_CONSIDERED;

}

"******************************************************************************

"* pcc data buffers enable

"******************************************************************************

equations

PccDataBufEn.oe = 3;

!PccEvenEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED &

(STATE_HOLD_OFF_CONSIDERED & HOLD_OFF_PERIOD #

STATE_NO_HOLD_OFF);

!PccOddEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED &

(STATE_HOLD_OFF_CONSIDERED & HOLD_OFF_PERIOD #

STATE_NO_HOLD_OFF);

"******************************************************************************

"* pcc data buffers direction

"******************************************************************************

equations

PccR_W~.oe = H;

PccR_W~ = R_W~;

"******************************************************************************

"* Dram Address lines.

"* These lines are conencted to the dram high order address lines A9 and A10

"* (if available). These lines change value according to the dram size and

"* port size.

"* The dram size is encoded from the presence detect lines (see definitions

"* above) and the port size is determined by the control register.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC821 датащи(PDF) 152 Page - NXP Semiconductors