MPC821 datasheet(41/242 Pages) NXP

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Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

ming" below:

4•8•1•1

SDRAM Initializing Procedure

After Power-up the SDRAM needs to be initialized in a certain manner, described below:

UPMB should be programmed with values described in TABLE 3-8. "UPMB Initializations

for MB811171622A-100 upto 32MHz" on page 26 or in TABLE 3-9. "UPMB Initializations

for MB811171622A-100, 32+MHz - 50MHz" on page 27.

Memory controller’s MPTPR, MBMR, OR4 and BR4 registers should be programmed ac-

cording to TABLE 3-6. "Memory Controller Initializations For 20Mhz" on page 22 or TABLE

3-3. "Memory Controller Initializations For 50Mhz" on page 19.

MAR should be set with proper value (0x48 for upto 32MHz or 0x88 for 32 - 50 MHz)

MCR should be written with 0x80808105 to run the MRS command programmed in loca-

tions 5 - 8 of UPMB.

MBMR’s TLFB field should be changed to 8, to constitute 8-beat refresh Bursts.

MCR should be written with 0x80808130 to run the refresh sequence (8 refresh cycles are

performed now)

MBMR’s TLFB field should be restored to 4, to provide 4-beat refresh Bursts for normal op-

eration. The SDRAM is initialized and ready for operation.

4•8•2

SDRAM Refresh

The SDRAM is refreshed using its auto-refresh mode. I.e., using UMPB’s periodic timer, a burst of

four auto-refresh commands is issued to the SDRAM every 62.4

µsec, so that all 2048 SDRAM rows

are refreshed within specified 32.8 msec.

TABLE 4-7. SDRAM’s Mode Register Programming

Value @ Frequency

SDRAM Option

50MHz

25MHz

Burst Length

Burst Type

Sequential

CAS Latency

Write Burst Length

Burst

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC821 датащи(PDF) 41 Page - NXP Semiconductors