MPC821 datasheet(30/242 Pages) NXP

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Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

4 - Functional Description

In this chapter the various modules combining the MPC8XXFADS are described to their design

details.

4•1

Reset & Reset - Configuration

There are several reset sources on the FADS:

1) Keep Alive Power-On ResetA

2) Regular Power On Reset

3) Manual Soft-Reset

4) Manual Hard-Reset

5) MPC Internal Sources. (See the appropriate Spec or U/M)

4•1•1

Keep Alive Power-On Reset

The Keep Alive Power - On Reset logic resides on the daughter board this since the Keep Alive power

bus is on that board and it also allows the use of the daughter board connected directly to a user’s

application.

4•1•2

Regular Power - On Reset

The regular power on reset operates in the same manner as the keep alive power-on reset, using a

similar device - the Seiko - S-8052ANY-NH-X with detection voltage of 2.595V to 2.805V. The refer-

ence voltage of this device is the MAIN VDDH bus of the MPC while the reset line assertedB, is the

HRESET* line.

When HRESET~ is asserted to the MPC, Hard-Reset configuration is made available to the MPC, via

BCSR0. See 4•1•6•2 "Hard Reset Configuration" on page 29 and TABLE 4-9. "BCSR0 Description"

on page 46.

4•1•3

Manual Soft Reset

To support application development not around the debug port and resident debuggers, a soft reset

push-button is provided. (SW2) Depressing that button, asserts the SRESET* pin of the MPC, gen-

erating a SOFT RESET sequence.

When the SRESET~ line is asserted to the MPC, the Soft-Reset configuration is made available to

the MPC, by the debug-port controller. See 4•1•6•3 "Soft Reset Configuration" on page 29.

4•1•4

Manual Hard Reset

To support application development not around the debug port, a Hard-Reset push-button is provid-

edC. When the Soft Reset push-button (SW2) is depressed in conjunction with the ABORT push-

button (SW1), the HRESET* line is asserted, generating a HARD RESET sequence. The button

sharing is for economy and board space saving and does not effect in any way, functionality.

4•1•5

MPC Internal Sources

Since the HRESET* and SRESET* lines of the MPC are open-drain and the on-board reset logic

drives these lines with open-drain gates, the correct operation of the internal reset sources of the

MPC is facilitated. As a rule, an internal reset source asserts HRESET* and / or SRESET* for a

minimum time of 512 system clocks. It is beyond the scope of this document to describe these

sources, however Debug-Port Soft / Hard Resets which are part of the development systemD, are

A. In fact generated on the daughter board.

B. Again not directly.

C. It is not a dedicated button.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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