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MPC821 датащи(PDF) 22 Page - NXP Semiconductors

номер детали MPC821
подробное описание детали  Design Specification
PDF  242 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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OPERATING INSTRUCTIONS
MPC8XXFADS Design Specification—Rev 0.1
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
a. Assuming 16.67 MHz BRGCLK.
b. Assuming 25MHz BRGCLK
c. For 50MHz BRGCLK
d. Assuming 32MHz BRGCLK.
MPTPR
All
Dram
SIMMs
Supported
0400
Divide by 16 (decimal)
MAMR
MB321BT08TASN60
40A21114a
60A21114b
C0A21114c
refresh clock divided by 40a or 60b or C0c, periodic
timer enabled, type 2 address multiplexing scheme, 1
cycle disable timer, GPL4 disabled for data sampling
edge flexibility, 1 loop read, 1 loop write, 4 beats
refresh burst.
MB322BT08TASN60
20A21114a
30A21114b
60A21114c
refresh clock divided by 20a or 30b or 60c, periodic
timer
enabled, type 2 address multiplexing scheme, 1 cycle
disable timer, GPL4 disabled for data sampling edge
flexibility, 1 loop read, 1 loop write, 4 beats refresh
burst.
MB324CT00TBSN60
40B21114a
60B21114b
C0B21114c
refresh clock divided by 40a or 60b or C0c, periodic
timer
enabled, type 3 address multiplexing scheme, 1 cycle
disable timer, GPL4 disabled for data sampling edge
flexibility, 1 loop read, 1 loop write, 4 beats refresh
burst.
MB328CT00TBSN60
20B21114a
30B21114b
60B21114c
refresh clock divided by 20a or 30b or 60c, periodic
timer
enabled, type 3 address multiplexing scheme, 1 cycle
disable timer, GPL4 disabled for data sampling edge
flexibility, 1 loop read, 1 loop write, 4 beats refresh
burst.
MBMR
MB811171622A-100
D0802114c
80802114d
refresh clock divided by D0 or 80, periodic timer
enabled, type 0 address multiplexing scheme, 1 cycle
disable timer, GPL4enabled, 1 loop read, 1 loop write,
4 beats refresh burst.
TABLE 3-3. Memory Controller Initializations For 50Mhz
Register
Device Type
Init Value [hex]
Description
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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