MPC821 datasheet(34/242 Pages) NXP

34 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

ing the UPM) are programmed accordingly.

Dram timing control is performed by UPMA of the MPC via CS2 (and CS3 for a dual-bank SIMM) re-

gion(s), i.e., RAS and CAS signals’ generation, during normalA access as well as during refresh

cycles and the necessary address multiplexingB are performed using UPMA. CS2* and CS3* signals

are buffered from the DRAM and each is split to 2 to overcome the capacitive load over the Dram

SIMM RAS lines.

The DRAM module may enabled / disabled at any time by writing the DRAMEN~ bit in BCSR1. See

TABLE 4-10. "BCSR1 Description" on page 48.

4•6•1

DRAM 16 Bit Operation

To enhance evaluation capabilities, support is given to Dram with 16-bit and 32-bit data bus width.

That way users can tailor dram configuration, to get best fit to their application requirements. When

the DRAM is in 16 bit mode, half of it can not be used, i.e., the memory portion that is connected to

data lines D(16:31).

To configure the DRAM for 16 bit data bus width operation, the following steps should be taken:

Set the Dram_Half_Word bit in BCSR1 to Half-Word. See TABLE 4-10. "BCSR1 Descrip-

tion" on page 48

The Port Size bits of BR2~ (and of BR3~ for a 2-bank DRAM simm) should be set to 16 bits.

The AM bits in OR2 register should be set to 1/2 of the nominal single-bank DRAM simm

volume or to 1/4 of the nominal dual-bank DRAM simm volume.

If a Dual-Bank DRAM simm is being used:

The Base-Address bits in BR3 register should be set to DRAM_BASE + 1/4

Nominal_Volume, that is, if a contiguous block of DRAM is desired.

The AM bits of OR3 register, should be set to 1/4 Nominal_Volume.

If the above is executed out of running code, than this code should not reside on the DRAM while

executing, otherwise, erratic behavior is likely to be demonstrated, resulting in a system crash.

4•6•2

DRAM Performance Figures

The projected performance figures for the dram are shown in TABLE 4-2. "Regular DRAM Perfor-

A. Normal i.e.: Single Read, Single Write, Burst Read & Burst Write.

B. Taking into account support for narrower bus widths.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC821 датащи(PDF) 34 Page - NXP Semiconductors