MPC821 datasheet(50/242 Pages) NXP

50 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

BCSR1 fields are described in TABLE 4-10. "BCSR1 Description" on page 48.

TABLE 4-10. BCSR1 Descriptiona

BIT

MNEMONIC

Function

PON

DEF

ATT.

FLASH_EN

Flash Enable. When this bit is active (low), the Flash memory module is

enabled on the local memory map. When in-active, the Flash memory is

removed from the local memory map and CS0~, to which the Flash memory

is connected may be used off-board via the expansion connectors.

R,W

DRAM_EN

Dram Enable. When this bit is active (low), the DRAM module is enabled

on the local memory map. When in-active, the DRAM is removed from the

local memory map and CS2~ and CS3~b, to which the DRAM is connected

may be used off-board via the expansion connectors.

R,W

ETHEN

Ethernet Port Enable. When asserted (low) the EEST connected to SCC1

is enabled. When negated (high) that EEST is in standby mode, while all its

system i/f signals are tri-stated.

R,W

IRDEN

Infra-Red Port Enable. When asserted (low), the Infra-Red transceiver,

connected to SCC2 is enabled. When negated, the Infra-Red transceiver is

put in shutdown mode. And SCC2 pins are available for off-board use via

the expansion connectors.

R,W

FLASH_CFG_EN

Flash Conﬁguration Enable. When this bit is asserted (low): (A) - the

Hard-Reset conﬁguration held in BCSR0 is NOT driven on the data bus

during Hard-Reset and (B) - conﬁguration data held at the 1’st word of the

ﬂash memory is driven to the data bus during Hard-Reset. c

R,W

CNT_REG_EN_P

ROTECT

Control Register Enable Protect. When this bit is active (low) the

BCSR_EN bit in that register can not be written. When in-active, BCSR_EN

may be written to remove the BCSR from the memory map. After any write

to BCSR1 this bit becomes active again. This bit is a read-onlyd bit on that

BCSR_EN

BCSR Enable. When this bit is active (low) the Board Control & Status

may not be read or written and its associated CS1~ is available for off-board

use via the expansion connectors.

This bit may be written with ’1’ only if

CNT_REG_EN_PROTECT bit is

negated (1).

When the BCSR is disabled it still continues to conﬁgure the board

according the last data held in it even during Hard-Reset.

R,W

RS232EN_1

RS232 port 1 Enable. When asserted (low) the RS232 transceiver for port

1, is enabled. When negated, the RS232 transceiver for port 1, is in standby

mode and the relevant MPC communication port pins are available for off-

board use via the expansion connectors.

R,W

PCCEN

PC Card Enable. When asserted (low), the on-board PCMCIA channel is

enabled, i.e., address and strobe buffers are enabled to / from the card.

When negated, all buffers to / from the PCMCIA channel are disabled

allowing off-board use of its associated lines.

R,W

PCCVCC0

Pc Card VCC Select 0. These signal in conjunction with PCCVCC1

determine the voltage applied to the PCMCIA card’s VCC. Possible values

are 0 / 3.3 / 5 V. For the encoding of these lines and their associated

voltages see

TABLE 4-11. "PCCVCC(0:1) Encoding" on page 49.

R,W

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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