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MPC821 датащи(PDF) 61 Page - NXP Semiconductors

номер детали MPC821
подробное описание детали  Design Specification
PDF  242 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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MPC821 датащи(HTML) 61 Page - NXP Semiconductors

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Functional Description
MPC8XXFADS Design Specification—Rev 0.1
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
has a 10 pin header connector matching the one on the FADS.
In this mode of operation, the on-board debug port controller, is connected to the target system’s
debug-port connector (see 4•12•1•1 "Debug Port Connection - Target System Requirements"
below). Since DSDO signal is driven by the MPC, it is a must, to remove the local MPC from its
socket, to avoid contention over this line.
When either the local MPC is removed from its socket or the daughter board is removed from the
FADS, all FADS’s modules are inaccessible, except for the debug-port controller. All module-enable
indications are darkened, regardless of their associated enable bits in the BCSR. Pull-up resistors are
connected to Chip-Select lines, so they do not float when the MPC is removed from its socket,
avoiding possible contention over data-bus lines.
4•12•1•1 Debug Port Connection - Target System Requirements
In order for a target system may be connected to the FADS, as a debug port controller, few measures
need to be taken on the target system:
1)
A 10-pin header connector should be made available, with electrical connections matching
FIGURE 4-8 "Standard Debug Port Connector" on page 61.
2)
Pull-down resistors, of app. 1K
Ω should be connected over DSDIA and DSCKA signals.
These resistors are to provide normalB operation, when a debug-port controller, is not con-
nected to the target system
3)
The debug-port should be enabled and routed to the desired pins. See the DBGC and
DBPC fields within the HARD-RESET configuration word.
4•12•2
Debug Port Control / Status Register
The control / status register is an 8 bit register (bit 7 stands for MSB). For the description of the ADI
A. Remember that the location of DSDI and DSCK is determined by the HARD-Reset configuration.
B. Normal - i.e., boot via CS0~.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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