MPC821 datasheet(78/242 Pages) NXP

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MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

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"******************************************************************************

"* Clock genrator Internals:

"******************************************************************************

DbgClkDivBy2

NODE istype 'reg, buffer';

DbgClkDivBy4

NODE istype 'reg, buffer';

DbgClkDivBy8

NODE istype 'reg, buffer'; " counter (divider) signals.

Cstr0

NODE istype 'reg, buffer';

Cstr1

NODE istype 'reg, buffer'; " Clock Safe Transition Register

"******************************************************************************

"* Reset active. (Active when at least one of the reset sources is active)

"******************************************************************************

PrimReset

NODE istype 'com';

" Primary Reset. Host initiated

D_PrimReset

NODE istype 'com';

" delayed Reset

DD_PrimReset

NODE istype 'com';

" double delayed primary reset.

Reset

NODE istype 'com';

" Interface reset.

PdaRst

NODE istype 'reg, buffer'; " MPC8XX continued / initiated.

" part of the status register.

"******************************************************************************

"* ADS_ACK, ADS_REQ auxiliary internal control signals

"******************************************************************************

S_HstReqNODE istype 'reg';

"sync. host req.

DS_HstReqNODE istype 'reg';

" double sync. host req.

S_D_C~NODE istype 'reg, buffer'; " synchronized data/ control selection

S_HstAckNODE istype 'reg, buffer'; " sync host ack

DS_HstAckNODE istype 'reg, buffer'; " double sync host ack

BundleDelay1,

BundleDelay0NODE istype 'reg, buffer';

"delay counter for bundle

" delay compensation

BndTmrExpNODE istype 'com';" terminal count for bundle

" delay timer.

PDOe NODE istype 'com';

"Mach to ADI data OE.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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