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MPC821 датащи(PDF) 71 Page - NXP Semiconductors |
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MPC821 датащи(HTML) 71 Page - NXP Semiconductors |
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71 / 242 page ![]() Support Information MPC8XXFADS Design Specification—Rev 0.1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE in TABLE 5-5. "P5 - Interconnect Signals" below 5•1•6 P6 - 5V Power Connector The 5V power connector - P6, is a 3-lead, two-part terminal block. The male part is soldered to the pcb, while the receptacle is connected to the power supply. That way fast connection / disconnection of power is facilitated and physical efforts are avoided on the solders, which therefore maintain solid connection over time. TABLE 5-5. P5 - Interconnect Signals Pin No. Signal Name Attribute Description 1 VFLS0 O Visible history FLushes Status 0. Indicates in conjunction with VFLS1, the number of instructions flushed from the core’s history buffer. Indicates also whether the MPC is in debug mode. If not using the debug port, may be configured for alternate function. When the FADS is disconnected from the ADI bundle, it may be FRZ signal, depended on J1’s position. 2 SRESET~ I/O Soft Reset line of the MPC. Active-low, Open-Drain. 3 GND Ground. 4 DSCK I/O Debug Serial Clock. Over the rising edge of which serial date is sampled by the MPC from DSDI signal. Over the falling edge of which DSDI is driven towards the MPC and DSDO is driven by the MPC. Configured on the MPC’s JTAG port. When the debug-port controller is on the local MPC or when the FADS is a debug-port controller for a target system - OUTPUT, when the FADI bundle is disconnected from the FADS - INPUT. 5 GND Ground 6 VFLS1 O See VFLS0. When the FADS is disconnected from the ADI bundle, it may be FRZ signal, depended on J1’s position. 7 HRESET~ I/O Hard Reset line of the MPC. Active-low, Open-Drain 8 DSDI I/O Debug Serial Data In of the debug port. Configured on the MPC’s JTAG port. When the debug-port controller is on the local MPC or when the FADS is a debug-port controller for a target system - OUTPUT, when the ADI bundle is disconnected from the FADS - INPUT. 9 V3.3 O 3.3V Power indication. This line is merely for indication. No significant power may be drawn from this line. 10 DSDO I/O Debug Serial Data Output from the MPC. Configured on the MPC’s JTAG port. When the debug-port controller is on the local MPC or when the ADI bundle is disconnected from the FADS - OUTPUT, when the FADS is a debug-port controller for a target system - INPUT. TABLE 5-6. P6 - Interconnect Signals Pin Number Signal Name Description 1 5V 5V input from external power supply. 2 GND GND line from external power supply. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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