MPC821 datasheet(18/242 Pages) NXP

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OPERATING INSTRUCTIONS

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

3•2•16

5V Indicator - LD11

The yellow 5V led, indicates the presence of the +5V supply at P6.

3•2•17

RUN Indicator - LD12

When the green RUN led - LD12 is lit, it indicates that the MPC is not in debug mode, i.e., VFLS0 &

VFLS1 == 0 (or FRZ == 0, which ever selected by J1).

3•2•18

AUXILARY Indicator LD13

This indication has no dedicated function over the FADS. It is meant to provide some visibility for

program behavior. It is controlled by the Signal Lamp bit in BCSR4.

3•2•19

FLASH ON - LD14

When the yellow FLASH ON led is lit, it indicates that the FLASH SIMM is enabled in the BCSR1

the flash is disabled and CS0~ may be used off-board via the expansion connectors.

3•2•20

DRAM ON - LD15

When the yellow DRAM ON led is lit, it indicates the DRAM SIMM is enabled in BCSR1. Therefore,

any access made to CS2~ (or CS3~) will hit on the DRAM. When it is dark, it indicates that either the

DRAM is disabled in BCSR1, enabling the use of CS2~ and CS3~ off-board via the expansion

connectors.

3•2•21

SDRAM ON - LD16

When the yellow SDRAM ON led is lit, it indicates the SDRAM is enabled in BCSR1. Therefore, any

access made to CS4~ (will hit on the SDRAM. When it is dark, it indicates that either the SDRAM is

disabled in BCSR1, enabling the use of CS4~ off-board via the expansion connectors.

3•2•22

PCMCIA ON - LD17

When the yellow PCMCIA ON led is lit, it indicates the following:

Address & strobe buffers are driven towards the PCMCIA card

Data buffers are driven to / from the PCMCIA card whenever CE1A~A or CE2A~B signals

are asserted.

Card status lines are driven towards the MPC from the PCMCIA card.

When it is dark, it indicates that all the above buffers are tri-stated and the pins associated with

PCMCIA channel AC, may be used off-board via the expansion connectors.

3•3

MEMORY MAP

All accesses to MPC8XXFADS’s memories are controlled by the MPC’s memory controller.

Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is

performed by the debug station, the debugger checks to see the size, delay and type of the DRAM

and FLASH SIMMs mounted on board and initializes the chip-selects accordingly. The DRAM,

A. Connected to CE1B~ for MPC823FADSDB.

B. Connected to CE2B~ for MPC823FADSDB.

C. Or B for MPC823FADSDB.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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