MPC821 datasheet(32/242 Pages) NXP

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Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

negated, if debug mode was enabled, DSCK is sampled again for debug-mode entry / non-entry.

DSDI is used to determine the debug port clock mode and is sampled after the negation of SRESET*.

The Soft Reset configuration is provided by the debug-port controller via the ADI I/F. Option is given

to enter debug mode directly or only after exception.

4•2

Local Interrupter

The only external interrupt which is applied to the MPC via its interrupt controller is the ABORT (NMI),

which is generated by a push-button. When this button is depressed, the NMI input to the MPC is

asserted. The purpose of this type of interrupt, is to support the use of resident debuggers if any is

made available to the FADS. All other interrupts to the MPC, are generated internally by the MPC’s

peripherals and by the debug port.

To support external (off-board) generation of an NMI, the IRQ0* line which is routed as an NMI input,

is driven by an open-drain gate. This allows for external h/w to also drive this line. If an external h/w

indeed does so, it is compulsory that IRQ0* is driven by an open-drain (or open-collector) gate.

4•3

Clock GeneratorA

There are 2 ways to clock the MPC on the MPC8XXFADS:

3 - 5MHz Clock generatorB connected to CLK4IN input. 1:5 PLL mode.

32.768 KHz crystal resonatorB via EXTAL-XTAL pair of the MPC, 1:513 initial PLL multi-

plication factor.

The selection between the above modes is done using Dip-switch (DS2 / 4) with dual functionality: it

is responsible to the combination driven to the MODCK lines during power-on reset and to the con-

nection of the appropriate capacitor between MPC’s XFC and VDDSYN lines to match the PLL’s mul-

tiplication factor. When 1:5 mode is selected, a capacitor of 5nF is connected, while when 1:513 mode

is selected a 0.68

µF capacitor is connected parallel to it via a TMOS gate. The capacitors’ values are

calculated to support a wider range of multiplication factors as possible.

When mode (2) above is selected, the output of the clock generator is gated from EXTCLK input and

driven to ’0’ constantly so that a jitter-free system clock is generated.

On-board logic is clocked by the MPC’s CLKOUT coming from the Daughter board. This clock is mul-

tiplexed with the debug port’s clock generator, so that on-board logic is always clocked, even when

the MPC is removed from its socketC.

4•4

Buffering

As the FADS meant to serve also as a hardware development platform, it is necessary to buffer the

MPC from the local bus, so the MPC’s capacitive drive capability is not wasted internally and remains

available for user’s off-board applications via the expansion connectors.

Buffers are provided for address and strobeD lines while transceivers are provided for data. Since the

capacitive load over dram’s address lines mightE exceed 200 pF, the dram address lines are sepa-

rately buffered. Use is done with 74LCX buffers which are 3.3V operated and are 5V tolerant. This

D. DSCK is configured at hard-reset to reside on the JTAG port.

A. Although this module resides on the DAUGHTER boards, it is described here, as it is common to all

MPC8XX supported.

B. Located On the Daughter Board.

C. When the FADS serves a debug station for target system.

D. If necessary.

E. Depended on dram SIMM’s internal structure.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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