MPC821 datasheet(47/242 Pages) NXP

47 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

14) USB Power Control.

15) Video Port Enable

16) Video Port Clock Select

17) Ethernet Port Control.

18) Dram Type / Size and Delay Identification.

19) Flash Size / Delay Identification.

20) External (off-board) tools identification or S/W option selection switch - DS1 status.

21) Daughter Board ID.

22) Mother Board Revision code

23) Daughter Board Revision code

Since all of the FADS’s modules are controlled by the BCSR and since they may be disabled in favor

of external hardware, the enable signals for these modules are presented at both the daughter board

connector and at the expansion connector over the daughter board, so that off- board hardware may

be mutually exclusive enabled with on-board modules.

4•11•1

BCSR Disable Protection Logic

The BCSR itself may be disabled in favor of off-board logic. To avoid accidental disable of the BCSR,

an event from which only power re-appliance recovers, protection logic is provided:

The BCSR_EN~ bit resides on BCSR1. This bit wakes-up active (low) during power-up and may not

be changedA unless BCSR_EN_PROTECT~ bit in BCSR3 is written with ’1’ previously.

After the BCSR_EN_PROTECT~ is written with ’1’ to unprotect the BCSR_EN~ bit there is only one

shot at disabling the BCSR, since, immediately after any write to BCSR1, BCSR_EN_PROTECT~ is

re-activated and BCSR_EN~ is re-protected and the disabling procedure has to be repeated if

desired.

4•11•2

BCSR0 - Hard Reset Configuration Register

BCSR0 is located at offset 0 on BCSR space. It may be read or written at any timeB. BCSR0 gets its

defaults upon MAINC Power-On reset. During Hard-Reset data contained in BCSR0 is driven on the

data bus to provide the Hard-Reset configuration for the MPC, this, if the

Flash_Configuration_Enable~ bit in BCSR1 is not active. BCSR0 may be written at any time to

change the Hard-Reset configuration of the MPC. The new values become valid when the next Hard-

Reset is issued to the MPC regardless of the Hard-Reset source. The description of BCSR0 bits is

D. For the MPC823 daughter board

E. For the MPC860SAR daughter board

F. For the MPC860T daughter board

A. It may be written but will not be influenced.

B. Provided that BCSR is not disabled.

C. I.e., when VDDH to the MPC is powered.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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