MPC821 datasheet(20/242 Pages) NXP

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OPERATING INSTRUCTIONS

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Ethernet controller.

Infra-Red Port Controller

General Purpose I/O signals.

The internal registers of the MPC must be programmed after Hard reset as described in the following

paragraphs. The addresses and programming values are in hexadecimal base.

For better understanding the of the following initializations refer to the MPC821 or to the MPC860

User’s Manual for more information.

3•4•1

Memory Controller Registers Programming

The memory controller on the MPC8XXFADS is initialized to 50 MHz operation. I.e., registers’ pro-

gramming is based on 50 MHZ timing calculation except for refresh timer which is initialized to

16.67Mhz, the lowest frequency at which the FADS may wake up. Since the FADS may be made to

wake-up at 25MHzA as well, the initializations are not efficient, since there are too many wait-states

inserted. Therefore, additional set of initialization is provided to support efficient 25MHz operation.

The reason for initializing the FADS for 50Mhz is to allow proper (although not efficient) FADS oper-

ation through all available FADS clock frequencies.

A. The only parameter which is initialized to the start-up frequency, is the refresh rate, which would have been

inadequate if initialized to 50Mhz while board is running at a lower frequency. Therefore, for best bus band-

width availability, refresh rate should be adapted to the current system clock frequency.

TABLE 3-2. SIU REGISTERS’ PROGRAMMING

Init Value[hex]

Description

SIUMCR

01032440

Internal arbitration, External master arbitration priority - 0, External arbitration

priority - 0, PCMCIA channel II pins - PCMCIA, Debug Port on JTAG port pins,

FRZ/IRQ6~ - FRZ, debug register - locked, No parity for non-CS regions, DP(0:3)/

IRQ(3:6)~ pins - DP(0:3), reservation disabled, SPKROUT - Tri-stated, BS_A(0:3)~

and WE(0:3)~ are driven just on their dedicated pins, GPL_B5~ enabled, GPL_A/

B(2:3)~ function as GPLs.

SYPCR

FFFFFF88

Software watchdog timer count - FFFF, Bus-monitor timing FF, Bus-monitor -

Enabled, S/W watch-dog - Freeze, S/W watch-dog - disabled, S/W watch-dog (if

enabled) causes NMI, S/W (if enabled) not prescaled.

TBSCR

00C2

No interrupt level, reference match indications cleared, interrupts disabled, no

freeze, time-base disabled.

RTCSC

00C2

Interrupt request level - 0, 32768 Hz source, second interrupt disabled, Alarm

interrupt disabled, Real-time clock - FREEZE, Real-time clock enabled.

PISCR

0082

No level for interrupt request, Periodic interrupt disabled, clear status, interrupt

disabled, FREEZE, periodic timer disabled.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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