MPC821 datasheet(63/242 Pages) NXP

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Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

FIGURE 4-8 Standard Debug Port Connector

4•12•3

Standard MPCXXX Debug Port Connector Pin Description

The pins on the standard debug port connector are the maximal group needed to support debug port

controllers for both the MPC5XX and MPC8XX families. Some of the pins are redundant for the

MPC8XX family but are necessary for the MPC5XX family.

4•12•3•1 VFLS(0:1)

These pins indicate to the debug port controller whether or not the MPC is in debug mode. When both

VFLS(0:1) are at ’1’, the MPC is in debug mode. These lines may serve alternate functions with the

MPC, in which case FRZ needs to selected, on either the FADS or target systemA.

4•12•3•2 HRESET*

This is the Hard-Reset bidirectional signal of the MPC. When this signal is asserted (low) the MPC

enters hard reset sequence which include hard reset configuration. This signal is made redundant

with the MPC8XX debug port controller since there is a hard-reset command integrated within the

debug port protocol. However, the local debug port controller uses this signal for compatibility with

MPC5XX existing boards and s/w.

4•12•3•3 SRESET*

This is the Soft-Reset bidirectional signal of the MPC8XX. On the MPC5XX it is an output. The debug

port configuration is sampled and determined on the rising-edgeB of SRESET* (for both processor

families). On the MPC8XX it is a bidirectional signal which may be driven externally to generate soft

reset sequence. This signal is in fact redundant regarding the MPC8XX debug port controller since

there is a soft-reset command integrated within the debug port protocol. However, the local debug

port controller uses this signal for compatibility with MPC5XX existing boards and s/w.

4•12•3•4 DSDI - Debug-port Serial Data In

Via the DSDI signal, the debug port controller sends its data to the MPC. The DSDI serves also a role

during soft-reset configuration. (See 4•1•6•3 "Soft Reset Configuration" on page 29).

4•12•3•5 DSCK - Debug-port Serial Clock

During asynchronous clock mode, the serial data is clocked into the MPC accordingC to the DSCK

clock. The DSCK serves also a role during soft-reset configuration. (See 4•1•6•3 "Soft Reset Config-

uration" on page 29).

4•12•3•6 DSDO - Debug-port Serial Data Out

DSDO is clocked out by the MPC according to the debug port clock, in parallelD with the DSDI being

clocked in. The DSDO serves also as "READY" signal for the debug port controller to indicate that

the debug port is ready to receive controller’s command (or data).

A. If a target system needs to use VFLS(0:1) alternate function, then, FRZ line should be connected to both

VFLS(0:1) pins on the debug port connector.

B. In fact that configuration is divided into 2 parts, the first is sampled 3 system clock cycles prior to the rising

edge of SRESET* and the second is sampled 8 clocks after that edge.

C. I.e., DSDI must meat setup / hold time to / from rising edge of the DSCK.

D. I.e., full-duplex communication.

VFLS0

SRESET

DSCK

VFLS1

DSDI

DSDO

GND

HRESET

VDD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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