MPC821 datasheet(35/242 Pages) NXP

35 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

mance Figures" on page 33 and in TABLE 4-3. "EDO DRAM Performance Figures" on page 33.

4•6•3

Refresh Control

The refresh to the dram is a CAS before RAS refresh, which is controlled by UPMA as well. The

refresh logic is clocked by the MPC’s BRG clock which is not influenced by the MPC’s low-power

divider.

a. Four-beat refresh burst.

b. Not including arbitration overhead.

a. Four-beat refresh burst.

b. Not including arbitration overhead.

TABLE 4-2. Regular DRAM Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

DRAM Delay [nsec]

Single Read

6634

Single Write

4433

Burst Read

6,2,3,2

6,3,2,3

3,2,2,2

4,2,2,2

Burst Write

4,2,2,2

3,1,2,2

3,2,2,2

Refresh

21a b

25a b

13a b

TABLE 4-3. EDO DRAM Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

DRAM Delay [nsec]

Single Read

6634

Single Write

4423

Burst Read

6,2,2,2

6,3,2,2

3,1,1,1

4,1,2,2

Burst Write

4,2,2,2

2,1,1,1

3,2,2,2

Refresh

21a b

25a b

13a b

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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