MPC821 datasheet(33/242 Pages) NXP

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Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

type of buffers reduces noise on board due to reduced transitions’ amplitude.

To further reduce noise and reflections, series resistors are placed over dram’s address and strobe

lines.

The data transceivers open only if there is an access to a validA B board address or during Hard -

Reset configurationC. That way data conflicts are avoided in case an off-board memory is read,

provided that it is not mapped to an address valid on board. It is the users’ responsibility to avoid such

errors.

4•5

Chip - Select Generator

The memory controller of the MPC is used as a chip-select generator to access on-boardD memories,

saving board’s area reducing cost, power consumption and increasing flexibility. To enhance off-

board application development, memory modules (including the BCSRx) may be disabled via

BCSR1E in favor of an external memory connected via the expansion connectors. That way, a CS

line may be used off-board via the expansion connectors, while its associated local memory is dis-

abled.

When a CS region is disabled via BCSR1, the local data transceivers do not open during access to

that region, avoiding possibleF contention over data lines.

The MPC’s chip-selects assignment to the various memories / registers on the FADS are as shown

in TABLE 4-1. "MPC8XXFADS Chip Selects’ Assignment" below:

4•6

DRAM

The MPC8XXFADS is provided with 4 MBytes of 60nsec delay EDO Dram SIMM. Support is given

to any 5V powered FPM / EDO Dram SIMM configured as 1M X32 upto 2 X 4M X 32, with 60 nsec

or 70nsec delay.

All dram configurations are supported via the Board Control & Status Register (BCSR), i.e., DRAM

size (4M to 32M) and delay (60 / 70 nsec) are read from BCSR2 and the associated registers (includ-

A. An address which covered in a Chip-Select region.

B. Except for SDRAM, which is Unbuffered.

C. To allow a configuration word stored in Flash memory become active.

D. And off-board. See further.

E. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply power to

the FADS.

F. During read cycles.

a. If exists.

TABLE 4-1. MPC8XXFADS Chip Selects’ Assignment

Chip Select:

Assignment

CS0*

Flash Memory

CS1*

BCSR

CS2*

DRAM Bank 1

CS3*

DRAM Bank 2a

CS4*

SDRAM

CS(5-7)*

Unused, user available

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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