MPC821 datasheet(31/242 Pages) NXP

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Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

regarded as such.

4•1•6

Reset Configuration

During reset the MPC device samples the state of some external pins to determine its operation

modes and pin configuration. There are 3 kinds of reset levels to the MPC each level having its own

configuration sampled:

1) Power - On Reset configuration

2) Hard Reset configuration

3) Soft Reset Configuration.

4•1•6•1

Power - On Reset Configuration

Just before PORESET* is negated by the external logic, the power-on reset configuration which

include the MODCK(1:2) pins is sampled. These pins determine the clock operation mode of the

MPC. Two clock modes are supported on the MPC8XXFADS:

1:5 PLL operation via on-board clock generator.

In this mode MODCK(1:2) are driven with ’11’ duringA power on reset.

1:513 PLL operation via on-board clock generator.

In this mode MODCK(1:2) are driven with ’00’. during power-on reset.

4•1•6•2

Hard Reset Configuration

During HARD reset sequence, when RSTCONF* pin is asserted, the MPC data bus state is sampled

to acquire the MPC’s hard reset configuration. The reset configuration word is driven by BCSR0 reg-

ister, defaults of which are set during power-on reset. The BCSR0 drives half of the configuration

word, i.e., data bits D(0:15) in which the reserved bits are designated RSRVxx. If the hard-reset con-

figuration is to be changedB, BCSR0 may be written with new values, which become valid after HARD

reset is applied to the MPC.

On the FADS, the RSTCONF* line is always driven during HARD reset, i.e., no use is possible with

the MPC’s internal HARD reset configuration defaults.

The system parameters to which BCSR0 defaults during power-on reset and are driven at hard-reset,

are listed below:

Arbitration: internal arbitration is selected.

Interrupt Prefix: The internal default is interrupt prefix at 0xFFF00000. It is overridden to

provide interrupt prefix at address 0, which is located within the DRAM.

Boot Disable: Boot is enabled.

Boot Port Size: 32 bit boot port size is selected.

Initial Internal Space Base: Immediately after HARD reset, the internal space is located at

$FF000000.

Debug pins configuration: PCMCIA port BC pins become PCMCIA port B pins.

Debug port pins configuration. Debug port pins are on the JTAG port.

External Bus Division Factor: 1:1 internal to external clocks’ frequencies ratio is selected.

4•1•6•3

Soft Reset Configuration

The rising edge of SRESET* is used to configure the development port. Before the negation of

SRESET*, DSCKD is sampled to determine for debug-mode enable / disable. After SRESET* is

D. And therefore mentioned.

A. The MODCK lines are in fact driven longer - by HRESET~ line.

B. With respect the FADS’s power-on defaults.

C. Where they exist.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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