MPC821 datasheet(82/242 Pages) NXP

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MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

VflsP

= [VflsP0,VflsP1];

BndDly

= [BundleDelay1, BundleDelay0];

"bundle delay

"compensation timer

TxReg

= [TxReg7..TxReg0];

RxReg

= [TxReg6,TxReg5,TxReg4,TxReg3,TxReg2,TxReg1,TxReg0,RxReg0];

AdiCtrlReg

= [DbgClkDivSel1, DbgClkDivSel0, StatusRequest~,

DiagLoopBack~,DebugEntry~];

AdiStatReg

= [PdaRst, TxError, InDebugMode, DbgClkDivSel1, DbgClkDivSel0,

StatusRequest~, DiagLoopBack~, DebugEntry~];

TxWordLen

= [TxWordLen3, TxWordLen2, TxWordLen1, TxWordLen0];

PortEn

= [AdsSel2,AdsSel1,AdsSel0,!AdsAddr2,!AdsAddr1,!AdsAddr0,

HostVcc,HstEn~];

"******************************************************************************

"* Select Logic definitions

"******************************************************************************

HOST_VCC_ACTIVE = 1;

HOST_EN~_ACTIVE = 0;

HOST_IS_ON

= ((HstEn~==HOST_EN~_ACTIVE) & (HostVcc==HOST_VCC_ACTIVE));

HOST_IS_OFF = !HOST_IS_ON;

BOARD_IS_SELECTED = 0;

ADS_IS_SELECTED = (AdsSelect~.fb==BOARD_IS_SELECTED) ;

"Data_Cntrl~ line levels.

DATA

= 1;

CONTROL = !DATA;

"******************************************************************************

"* Reset Logic definitions

"******************************************************************************

ADS_HARD_RESET_ACTIVE

= 1;

ADS_SOFT_RESET_ACTIVE

= 1;

"******************************************************************************

"* Clock Logic definitions

"******************************************************************************

SELECT_CHANGE_ALLOWED =

(DbgClkDiv.fb == 0);

DEBUG_CLOCK_DIV_BY_1 = (Cstr.fb == 0);

DEBUG_CLOCK_DIV_BY_2 = (Cstr.fb == 1);

DEBUG_CLOCK_DIV_BY_4 = (Cstr.fb == 2);

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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