HC705C9AGRSSLASHD datasheet(105/157 Pages) NXP

105 / 157 page

General Release Specification

SPI Registers

MC68HC705C9A — Rev. 2.0

Serial Peripheral Interface

10.6 SPI Registers

Three registers in the SPI provide control, status, and data storage

functions. These registers are called the serial peripheral control register

(SPCR), serial peripheral status register (SPSR), and serial peripheral

data I/O register (SPDR) and are described in the following paragraphs.

10.6.1 Serial Peripheral Control Register (SPCR)

The SPI control register, shown in Figure 10-4, controls these functions:

•

Enables SPI interrupts

•

Enables the SPI system

•

Selects between standard CMOS or open drain outputs for port D

(C9A mode only)

•

Selects between master mode and slave mode

•

Controls the clock/data relationship between master and slave

•

Determines the idle level of the clock pin

SPIE — Serial Peripheral Interrupt Enable

This read/write bit enables SPI interrupts. Reset clears the SPIE bit.

1 = SPI interrupts enabled

0 = SPI interrupts disabled

SPE — Serial Peripheral System Enable

This read/write bit enables the SPI. Reset clears the SPE bit.

1 = SPI system enabled

0 = SPI system disabled

$000A

Bit 7

654321

Bit 0

Read:

SPIE

SPE

DWOM

(C9A)

MSTR

CPOL

CPHA

SPR1

SPR0

Write:

Reset:

000001

U = Undetermined

Figure 10-4. SPI Control Register (SPCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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