HC705C9AGRSSLASHD datasheet(103/157 Pages) NXP

103 / 157 page

General Release Specification

Functional Description

MC68HC705C9A — Rev. 2.0

Serial Peripheral Interface

10.5 Functional Description

Figure 10-2 shows a block diagram of the serial peripheral interface

circuitry. When a master device transmits data to a slave via the MOSI

line, the slave device responds by sending data to the master device via

the master’s MISO line. This implies full duplex transmission with both

data out and data in synchronized with the same clock signal. Thus, the

byte transmitted is replaced by the byte received and eliminates the

need for separate transmit-empty and receive-full status bits. A single

status bit (SPIF) is used to signify that the I/O operation has been

completed.

Figure 10-2. Serial Peripheral Interface Block Diagram

543210

SPE

SPIE

SPI CONTROL REGISTER (SPCR)

MSTR

CPOL

CPHA

SPR1

SPR2

$000A

WCOL

SPIF

SPI STATUS REGISTER (SPSR)

MODF

$000B

BIT 6

BIT 7

SPI DATA REGISTER (SPDR)

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

$000C

DWOM

SPI SHIFT REGISTER

DIVIDER

CLOCK

LOGIC

SPDR ($000C)

7 6 5 4 3 2 1 0

MODF

WCOL

SPIF

SPR1

SPR0

CPOL

CPHA

MSTR

SPE

SPIE

PD3/

MOSI

PD2/

MISO

÷ 2

÷ 32

÷ 16

÷ 4

SELECT

SPI

CONTROL

INTERNAL DATA BUS

MSTR

INTERNAL

CLOCK

(XTAL

÷2)

SPI CLOCK (MASTER)

SPI INTERRUPT REQUEST

PD4/

SCK

PD5/

(SLAVE)

SPI

(MASTER)

CLOCK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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