HC705C9AGRSSLASHD datasheet(12/157 Pages) NXP

12 / 157 page

General Release Speciﬁcation

MC68HC705C9A — Rev. 2.0

List of Figures

Figure

Title

Page

7-1

Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7-2

Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8-1

Capture/Compare Timer Block Diagram . . . . . . . . . . . . . . 68

8-2

Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . 70

8-3

Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . 72

8-4

Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . 73

8-5

Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . 74

8-6

Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . 75

8-7

Output Compare Registers (OCRH and OCRL). . . . . . . . . 76

9-1

Serial Communications Interface Block Diagram . . . . . . . . 81

9-2

Rate Generator Division . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9-3

Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9-4

SCI Examples of Start Bit Sampling Techniques . . . . . . . . 87

9-5

SCI Sampling Technique Used on All Bits . . . . . . . . . . . . . 87

9-6

SCI Artificial Start Following a Frame Error . . . . . . . . . . . . 89

9-7

SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . 89

9-8

SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . 90

9-9

SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . 91

9-10

SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . 92

9-11

SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . 94

9-12

Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . 96

10-1

Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 101

10-2

Serial Peripheral Interface Block Diagram . . . . . . . . . . . . 103

10-3

Serial Peripheral Interface

Master-Slave Interconnection. . . . . . . . . . . . . . . . . . . . . . 104

10-4

SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . 105

10-5

SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10-6

PI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . 109

12-1

Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12-2

Maximum Supply Current vs Internal

Clock Frequency, V

DD = 5.5 V . . . . . . . . . . . . . . . . . . . . . 136

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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