HC705C9AGRSSLASHD datasheet(83/157 Pages) NXP

83 / 157 page

General Release Specification

Functional Description

MC68HC705C9A — Rev. 2.0

Serial Communications Interface (SCI)

interrupts are enabled). The transfer of data to the transmit data shift

is transmitted least significant bit first. Upon completion of data

transmission, the transmission complete flag (TC) in the SCSR is set

(provided no pending data, preamble, or break is to be sent) and an

interrupt is generated (if the transmit complete interrupt is enabled). If

the transmitter is disabled, and the data, preamble, or break (in the

transmit data shift register) has been sent, the TC bit will be set also.

This will also generate an interrupt if the transmission complete interrupt

enable bit (TCIE) is set. If the transmitter is disabled during a

transmission, the character being transmitted will be completed before

the transmitter gives up control of the TDO pin.

When SCDR is read, it contains the last data byte received, provided

that the receiver is enabled. The receive data register full flag bit (RDRF)

in the SCSR is set to indicate that a data byte has been transferred from

the input serial shift register to the SCDR; this will cause an interrupt if

the receiver interrupt is enabled. The data transfer from the input serial

shift register to the SCDR is synchronized by the receiver bit rate clock.

The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR

may be set if data reception errors occurred.

An idle line interrupt is generated if the idle line interrupt is enabled and

the IDLE bit (which detects idle line transmission) in SCSR is set. This

allows a receiver that is not in the wakeup mode to detect the end of a

message, or the preamble of a new message, or to re-synchronize with

the transmitter. A valid character must be received before the idle line

condition or the IDLE bit will not be set and idle line interrupt will not be

generated.

Figure 9-2. Rate Generator Division

OSC FREQ

(fOSC)

÷2

BUS FREQ

(fOP)

SCP0–SCP1

SCI PRESCALER

SELECT

SCR0–SCR2

SCI RATE

SELECT

÷16

SCI TRANS

CLOCK (TX)

SCI RECEIVE

CLOCK (RT)

CONTROL

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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