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HC705C9AGRS/D датащи(PDF) 54 Page - NXP Semiconductors |
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HC705C9AGRS/D датащи(HTML) 54 Page - NXP Semiconductors |
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54 / 157 page ![]() General Release Specification Computer Operating Properly (COP) Reset MC68HC705C9A — Rev. 2.0 Resets 5.5 Computer Operating Properly (COP) Reset This device includes a watchdog COP feature which guards against program run-away failures. A timeout of the computer operating properly (COP) timer generates a COP reset. The COP watchdog is a software error detection system that automatically times out and resets the MCU if not cleared periodically by a program sequence. This device includes two COP types, one for C12A compatibility and the other for C9A compatibility. When configured as a C9A the COP can be enabled by user software by setting COPE in the C9A COP control register (C9ACOPCR). When configured as a C12A, the COP is enabled prior to operation by programming the C12COPE bit in the C12A mask option register (C12MOR). The function and control of both COPs is detailed below. 5.6 MC68HC05C9A Compatible COP This COP is controlled with two registers; one to reset the COP timer and the other to enable and control COP and clock monitor functions. Figure 5-3 shows a block diagram of the MC68HC05C9A COP. Figure 5-3. C9A COP Block Diagram ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷4 ÷4 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 213 215 217 219 221 COPRST CM0 CM1 16 BIT TIMER SYSTEM INTERNAL CPU CLOCK COP Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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