HC705C9AGRSSLASHD datasheet(62/157 Pages) NXP

номер детали	HC705C9AGRS/D

подробное описание детали	General Release Specification

PDF	157 Pages

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производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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General Release Speciﬁcation

Wait Mode

MC68HC705C9A — Rev. 2.0

Low-Power Modes

Figure 6-1. Stop Recovery Timing Diagram

6.4 Wait Mode

The WAIT instruction places the MCU in a low-power consumption

mode, but the wait mode consumes more power than the stop mode. All

CPU action is suspended, but the timer, SCI, SPI, and the oscillator

remain active. Any interrupt or reset will cause the MCU to exit the wait

mode.

During wait mode, the I bit in the CCR is cleared to enable interrupts. All

other registers, memory, and input/output lines remain in their previous

state. The timer, SCI, and SPI may be enabled to allow a periodic exit

from the wait mode.

3FFE

3FFF

INTERNAL

ADDRESS

BUS

INTERNAL

CLOCK

IRQ

RESET

OSC1

ILCH

4064 t

cyc

RESET OR INTERRUPT

VECTOR FETCH

LIH

NOTES:

1. Represents the internal gating of the OSC1 pin

2. IRQ pin edge-sensitive mask option

3. IRQ pin level and edge-sensitive mask option

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705C9AGRS/D датащи(PDF) 62 Page - NXP Semiconductors