HC705C9AGRSSLASHD datasheet(57/157 Pages) NXP

номер детали	HC705C9AGRS/D

подробное описание детали	General Release Specification

PDF	157 Pages

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производитель	NXP [NXP Semiconductors]

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General Release Specification

MC68HC05C9A Compatible COP

MC68HC705C9A — Rev. 2.0

Resets

COPE — COP Enable

This bit is readable any time. COPE, CM1, and CM0 together may be

written with a single write, only once, after reset. This bit is cleared by

reset.

1 = COP enabled

0 = COP disabled

CM1 — COP Mode Bit 1

Used in conjunction with CM0 to establish the COP timeout period,

this bit is readable any time. COPE, CM1, and CM0 together may be

written with a single write, only once, after reset. This bit is cleared by

reset.

CM0 — COP Mode Bit 0

Used in conjunction with CM1 to establish the COP timeout period,

this bit is readable any time. COPE, CM1, and CM0 together may be

written with a single write, only once, after reset. This bit is cleared by

reset.

Bits 7–5 — Not Used

These bits always read as zero.

Table 5-1. COP Timeout Period

CM1

CM0

fop/2

15 Divide By

Timeout Period

(fosc = 2.0 MHz)

Timeout Period

(fosc = 4.0 MHz)

32.77 ms

16.38 ms

131.07 ms

65.54 ms

524.29 ms

262.14 ms

2.097 sec

1.048 sec

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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