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HC705C9AGRS/D датащи(PDF) 86 Page - NXP Semiconductors |
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HC705C9AGRS/D датащи(HTML) 86 Page - NXP Semiconductors |
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86 / 157 page ![]() General Release Specification Idle Line Wakeup MC68HC705C9A — Rev. 2.0 Serial Communications Interface (SCI) 9.9 Idle Line Wakeup In idle line wakeup mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for 10 (or 11) full bit times. Systems using this type of wakeup must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message. 9.10 Address Mark Wakeup In address mark wakeup, the most significant bit (MSB) in a character is used to indicate whether it is an address (logic one) or data (logic zero) character. Sleeping receivers will wake up whenever an address character is received. Systems using this method for wakeup would set the MSB of the first character of each message and leave it clear for all other characters in the message. Idle periods may be present within messages and no idle time is required between messages for this wakeup method. 9.11 Receive Data In (RDI) Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred to as the RT rate in Figure 9-4 and as the receiver clock in Figure 9-6. The receiver clock generator is controlled by the baud rate register; however, the SCI is synchronized by the start bit, independent of the transmitter. Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sampled three times at RT intervals 8 RT, 9 RT, and 10 RT (1 RT is the position where the bit is expected to start), as shown in Figure 9-5. The value of the bit is determined by voting logic which takes the value of the majority of the samples. A noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not agree. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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