HC705C9AGRSSLASHD datasheet(22/157 Pages) NXP

номер детали	HC705C9AGRS/D

подробное описание детали	General Release Specification

PDF	157 Pages

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производитель	NXP [NXP Semiconductors]

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General Release Speciﬁcation

Mask Options

MC68HC705C9A — Rev. 2.0

General Description

1.5 Mask Options

The following two mask option registers are used to select features

controlled by mask changes on the MC68HC05C9A and the

MC68HC05C12A:

•

Port B Mask Option Register (PBMOR)

•

C12 Mask Option Register (C12MOR)

The mask option registers are EPROM locations which must be

programmed prior to operation of the microcontroller.

1.5.1 Port B Mask Option Register (PBMOR)

The PBMOR register, shown in Figure 1-2, contains eight

programmable bits which determine whether each port B bit (when in

input mode) has the pullup and interrupt enabled. The port B interrupts

share the vector and edge/edge-level sensitivity with the IRQ pin. For

more details, (see 4.4 External Interrupt (IRQ or Port B)).

PBPU7–PBPU0 — Port B Pullup/Interrupt Enable Bits

1 = Pullup and CPU interrupt enabled

0 = Pullup and CPU interrupt disabled

NOTE:

The current capability of the port B pullup devices is equivalent to the

MC68HC05C9A, which is less than the MC68HC05C12A.

$3FF0

Bit 7

654321

Bit 0

PBPU7

PBPU6

PBPU5

PBPU4

PBPU3

PBPU2

PBPU1

PBPU0

Figure 1-2. Port B Mask Option Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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