HC705C9AGRSSLASHD datasheet(58/157 Pages) NXP

номер детали	HC705C9AGRS/D

подробное описание детали	General Release Specification

PDF	157 Pages

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производитель	NXP [NXP Semiconductors]

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General Release Speciﬁcation

MC68HC05C12A Compatible COP

MC68HC705C9A — Rev. 2.0

Resets

5.7 MC68HC05C12A Compatible COP

This COP is implemented with an 18-bit ripple counter. This provides a

timeout period of 64 milliseconds at a bus rate (fop) of 2 MHz. If the COP

should time out, a system reset will occur and the device will be

re-initialized in the same fashion as a power-on reset or reset.

5.8 MC68HC05C12A Compatible COP Clear Register

The COP clear register, shown in Figure 5-6, resets the C12A COP

counter.

COPC — Computer Operating Properly Clear

Preventing a COP reset is achieved by writing a zero to the COPC bit.

This action will reset the counter and begin the timeout period again.

The COPC bit is bit 0 of address $3FF0. A read of address $3FF0 will

result in the data programmed into the mask option register PBMOR.

5.9 COP During Wait Mode

Either COP will continue to operate normally during wait mode. The

software must pull the device out of wait mode periodically and reset the

COP to prevent a system reset.

$3FF0

Bit 7

6543

Bit 0

Read:

Write:

COPC

Reset:

= Unimplemented

U = Undetermined

Figure 5-6. COP Clear Register (COPCLR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705C9AGRS/D датащи(PDF) 58 Page - NXP Semiconductors