HC705C9AGRSSLASHD datasheet(108/157 Pages) NXP

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General Release Speciﬁcation

SPI Registers

MC68HC705C9A — Rev. 2.0

Serial Peripheral Interface

WCOL — Write Collision

The write collision bit is set when an attempt is made to write to the

serial peripheral data register while data transfer is taking place. If

CPHA is zero, a transfer is said to begin when SS goes low and the

transfer ends when SS goes high after eight clock cycles on SCK.

When CPHA is one, a transfer is said to begin the first time SCK

becomes active while SS is low and the transfer ends when the SPIF

flag gets set. Clearing the WCOL bit is accomplished by reading the

SPSR (with WCOL set) followed by an access to SPDR.

MODF — Mode Fault

The mode fault flag indicates that there may have been a multi-master

conflict for system control and allows a proper exit from system

operation to a reset or default system state. The MODF bit is normally

clear, and is set only when the master device has its SS pin pulled

low. Setting the MODF bit affects the internal serial peripheral

interface system in the following ways.

An SPI interrupt is generated if SPIE = 1.

The SPE bit is cleared. This disables the SPI.

The MSTR bit is cleared, thus forcing the device into the slave

mode.

Clearing the MODF bit is accomplished by reading the SPSR (with

MODF set), followed by a write to the SPCR. Control bits SPE and

MSTR may be restored by user software to their original state during

this clearing sequence or after the MODF bit has been cleared. When

configured as an MC68HC05C9A, it is also necessary to restore

DDRD after a mode fault.

Bits 5 and 3–0 — Not Implemented

These bits always read zero.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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