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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HC705C9AGRS/D датащи(PDF) 48 Page - NXP Semiconductors |
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HC705C9AGRS/D датащи(HTML) 48 Page - NXP Semiconductors |
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48 / 157 page  General Release Specification Timer Interrupt MC68HC705C9A — Rev. 2.0 Interrupts 4.5 Timer Interrupt Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF8 and $3FF9. 4.6 SCI Interrupt Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF6 and $3FF7. 4.7 SPI Interrupt Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF4 and $3FF5. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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