HC705C9AGRSSLASHD datasheet(68/157 Pages) NXP

68 / 157 page

General Release Speciﬁcation

Timer Operation

MC68HC705C9A — Rev. 2.0

Capture/Compare Timer

Figure 8-1. Capture/Compare Timer Block Diagram

8.3 Timer Operation

The core of the capture/compare timer is a 16-bit free-running counter.

The counter provides the timing reference for the input capture and

output compare functions. The input capture and output compare

functions provide a means to latch the times at which external events

occur, to measure input waveforms, and to generate output waveforms

and timing delays. Software can read the value in the 16-bit free-running

counter at any time without affecting the counter sequence.

Because of the 16-bit timer architecture, the I/O registers for the input

capture and output compare functions are pairs of 8-bit registers.

INPUT

CAPTURE

CLOCK

INTERNAL BUS

OUTPUT

COMPARE

HIGH

BYTE

LOW

BYTE

$16

$17

÷4

INTERNAL

PROCESSOR

16-BIT FREE

RUNNING

COUNTER

ALTERNATE

8-BIT

BUFFER

HIGH

BYTE

LOW

BYTE

$1A

$1B

$18

$19

HIGH

BYTE

LOW

BYTE

$14

$15

OUTPUT

COMPARE

CIRCUIT

OVERFLOW

DETECT

CIRCUIT

EDGE

DETECT

CIRCUIT

TIMER

STATUS

REG.

ICF OCF TOF $13

ICIE

IEDG OLVL

OUTPUT

LEVEL

REG.

RESET

TIMER

CONTROL

REG.

$12

OUTPUT

LEVEL

(TCMP)

INTERRUPT CIRCUIT

TOIE

OCIE

EDGE

INPUT

(TCAP)

CLK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705C9AGRS/D датащи(PDF) 68 Page - NXP Semiconductors

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