HC705C9AGRSSLASHD datasheet(46/157 Pages) NXP

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General Release Speciﬁcation

Introduction

MC68HC705C9A — Rev. 2.0

Interrupts

NOTE:

The current instruction is the one already fetched and being operated on.

When the current instruction is complete, the processor checks all

pending hardware interrupts. If interrupts are not masked (CCR I bit

clear) and if the corresponding interrupt enable bit is set, the processor

proceeds with interrupt processing; otherwise, the next instruction is

fetched and executed.

If an external interrupt and a timer, SCI, or SPI interrupt are pending at

the end of an instruction execution, the external interrupt is serviced first.

The SWI is executed the same as any other instruction, regardless of the

I-bit state.

Table 4-1 shows the relative priority of all the possible interrupt sources.

Figure 4-1 shows the interrupt processing flow.

Table 4-1. Vector Addresses for Interrupts and Resets

Function

Source

Local

Mask

Global

Mask

Priority

(1 = Highest)

Vector

Address

Reset

Power-On-Reset

None

$3FFE–$3FFF

RESET Pin

COP Watchdog

Software

Interrupt

(SWI)

User Code

None

Same Priority

As Instruction

$3FFC–$3FFD

External

Interrupt

IRQ Pin

Port B Pins

None

I Bit

$3FFA–$3FFB

Timer

Interrupts

ICF Bit

ICIE Bit

I Bit

$3FF8–$3FF9

OCF Bit

OCIE Bit

TOF Bit

TOIE Bit

SCI

Interrupts

TDRE Bit

TCIE Bit

I Bit

$3FF6–$3FF7

TC Bit

RDRF Bit

RIE Bit

OR BIt

IDLE Bit

ILIE Bit

SPI

Interrupts

SPIF Bit

SPIE

I Bit

$3FF4–$3FF5

MODF Bit

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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