DA16200 datasheet(102/154 Pages) RENESAS

102 / 154 page

DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

102 of 153

Bit

Mode

Symbol

Description

Reset

2'b00: PCM_8

PCM_8

R/W

MUTE

If set, SDATA output assert “0”

1'b0

R/W

HALF_DELAY

Relationship between FS and SCLK

1: Falling edge

1'b0

R/W

PCMM

If set, PCM Mode is enabled

1'b1

R/W

Right_Align

If set, PCM data output right is enabled

1'b0

R/W

ENDIAN

SDATA Output mode

1 = Big endian

0 = Little endian

1'b0

R/W

MCLK_INV

If set, MCLK inversion

1'b1

R/W

LRCK_INV

If set, LRCK inversion

1'b0

R/W

I2S_Enalbe

If set, I2S block is enabled

1'b0

R/W

CLK_DOWN

If set, output clock signals, LRCK/BCLK/SCLK, assert

“0”

1'b0

Table 148: I2S_CTRL1 (0x4001_4004)

Bit

Mode

Symbol

Description

Reset

15:8

Reserved

R/W

RxFIFO_Rst

Master Rx FIFO reset

0: reset

1: normal

1'b0

R/W

Left_Justify

Rx decoding left justified

1'b0

R/W

Rx_Mode

Rx decoding edge

0: rising edge @SCLK

1: falling edge

1'b0

R/W

Mst_RxEn

Master Rx load enable signal

0: Tx enable

1: Rx enable

1'b0

R/W

Rx_ChSel

Rx data channel selection

0=Rx decoding only Right channel

1=Rx decoding only Left channel

1'b0

R/W

LR_ChSel

Left/Right Channel selection

1: first data comes out LRCK high

0: first data comes out LRCK low duration

1'b0

Table 149: I2S_DATA (0x4001_4008)

Bit

Mode

Symbol

Description

Reset

31:0

R/W

I2S_DATA

write data @ Tx

read data @ Rx

32'b0000

DA16200 датащи(PDF) 102 Page - Renesas Technology Corp

DA16200 датащи(HTML) 102 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL