DA16200 datasheet(106/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

106 of 153

Bit

Mode

Symbol

Description

Reset

31:16

Reserved

R/W

ALL_RST

Reset All H/W Circuit Control

0: Normal Operation

1: Reset

1'b0

R/W

HIF_RST

Control Register and H/W Circuit Control

0: Normal Operation

1: Reset

1'b0

R/W

CSM_RST

Command State Machine Reset Control

0: Normal Operation

1: Reset

1'b0

R/W

DSM_RST

Data State Machine Reset Control

0: Normal Operation

1: Reset

1'b0

R/W

STOP_XTR

Immediately Stop the Ongoing Data Transfer

0: Normal Operation

1: Immediately Stop the Ongoing Data Transfer

1'b0

9:8

R/W

WR_STR_CTL[1:0]

Data Transfer Start Control for Write Operation

2'b0x: The starting of write data is triggered by TRIG

bit of HIF_CMD_IDX register

2'b10: Not trigger the starting for write data

operation

2'b11: Trigger the starting for write data operation

2'b00

R/W

HIF_PWR_CTL

Host Interface Power Control

0: Turn-off host interface power

1: Turn-on host interface power

1'b0

Reserved

R/W

CDI_POL_CTL

Card Detect Input Polarity Control

0: low active

1: high active

1'b0

R/W

RD_CRC_CHK

Read Data CRC Check Control

0: Disable

1: Enable

1'b1

R/W

RSP_CRC_CK

Response CRC Check Control

0: Disable

1: Enable

1'b1

R/W

BUS_4BIT

4 Bit Data Bus Mode

0: 1-bit Mode

1: 4-bit Mode

1'b0

Bit

Mode

Symbol

Description

Reset

R/W

HIGH_SPD

High Speed Timing Mode

0: Default Speed Timing Mode (SDC and

SDATA[3:0] signals output at clock falling edge)

1: High Speed Timing Mode (SDC and SDATA[3:0]

signals output at clock rising edge)

1'b0

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