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DA16200 датащи(PDF) 101 Page - Renesas Technology Corp

номер детали DA16200
подробное описание детали  Ultra Low Power Wi-Fi SoC
PDF  154 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA16200 датащи(HTML) 101 Page - Renesas Technology Corp

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DA16200
Ultra Low Power Wi-Fi SoC
Datasheet
Revision 3.6
04-Jan-2023
CFR0011-120-00
101 of 153
© 2023 Renesas Electronics
Bit
Mode
Symbol
Description
Reset
0 = UART RS-485 mode is disabled
1 = UART RS-485 mode is enabled
10.3 I2S Register
DA16200 provides an I2S interface that has both I2S transmission and reception functions. However,
the transmission and reception functions cannot be used at the same time. The transmit and receive
functions can be selected by setting the register.
When the I2S clock divider register is used, the internal PLL clock can be variably applied to the I2S
clock source. The available I2S clock source is 24/48 MHz. There is also a way to apply the I2S clock
source directly from the outside with the use of the GPIO pin.
Table 146: I2S Registers Overview
Address
Register
Description
Common control for I2S Pin Status
0x4001_4000
I2S_CTRL0
I2S Control Register 0
0x4001_4004
I2S_CTRL1
I2S Control Register 1
0x4001_4008
I2S_DATA
I2S Data Register
0x4001_400C
I2S_STATUS
I2S Status Register
0x4001_4010
Reserved
0x4001_4014
I2S_IMASK
I2S Interrupt Mask Register
0x4001_4018
Reserved
0x4001_401C
Reserved
0x4001_4020
I2S_ICR
I2S Rx Overrun Interrupt Clear Register
0x4001_4024
I2S_DMACR
I2S DMA Enable Register
0x5000_1314
I2S_CLK_SEL
I2S Clock divider Register
Table 147: I2S_CTRL0 (0x4001_4000)
Bit
Mode
Symbol
Description
Reset
15:12
R/W
CLK_DIV
I2S_SCLK control factor
4'h0: I2SCLK/2
4'h1: I2SCLK/4
4'h3: I2SCLK/8
4'h7: I2SCLK/16
4'b0011
11
R/W
STEREO
1 = Stereo
0 = Mono
1'b0
10:9
R/W
PCM_BW
PCM bus width for Tx / Rx
Tx
Rx
2'b11: PCM_24
PCM_32
2'b10: PCM_20
PCM_24/PCM_20
2'b01: PCM_16
PCM_16
2'b00



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