CS47L35 datasheet(190/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.16 Clocking and Sample Rates

The DSPCLK signal is enabled by setting DSP_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK, or FLL) must

be enabled before setting DSP_CLK_ENA. This bit must be cleared when reconfiguring the clock sources.

In a typical application, DSPCLK and SYSCLK are derived from a single FLL source. In this case, one of the nominal

DSPCLK frequencies is likely to be applicable (see Table 4-93). Note that there is no requirement for DSPCLK to be

synchronized to SYSCLK. The DSPCLK controls the software execution in the DSP cores; audio outputs from the DSP

cores are synchronized to SYSCLK, regardless of the applicable DSPCLK rate.

The DSPCLK signal is the reference clock for the DSP cores and DSP peripherals on the CS47L35. All of the

DSPCLK-dependent functions should be disabled if DSPCLK is not enabled. The DSPCLK_ENA bit must be set before

enabling any DSPCLK-dependent function, and all the dependent functions should be disabled before clearing the

DSPCLK_ENA bit.

The DSPCLK-dependent subsystems are referenced below; if one or more of the following conditions is met, then the

DSPCLK signal is required, and should not be interrupted or reconfigured.

• DSP core enabled (DSPn_CORE_ENA = 1)

• DSP DMA function enabled (DSPn_[WDMA/RDMA]_CHANNEL_ENABLE > 0x00)

• DSP core in JTAG mode

• Master Interface active (MIF1_BUSY_STS = 1)

• Timer enabled (TIMERn_RUNNING_STS = 1)

If reconfiguration of the DSPCLK source or frequency is required, and it is not possible to disable all of the

DSPCLK-dependent functions, then the following control requirements must be applied to reconfigure DSPCLK:

• Clear DSP_CLK_ENA to 0

•Wait 34

s (only required if a Timer is enabled)

• Update DSP_CLK_SRC and DSP_CLK_FREQ_RANGE, and set DSP_CLK_ENA = 1. (These must be applied in

a single register write operation)

• Note that, if a DSP core is enabled, DMA function is enabled, DSP core is in JTAG mode, or a Master Interface is

active, then no other register read/write actions (either by Control Interface or by DSP firmware access) can be

permitted during this sequence.

• If a Timer is enabled, but no DSP core, DMA, JTAG, or MIF is active, then DSPCLK can be stopped at any time.

The minimum wait time of 34

s is required before changing DSP_CLK_SRC or DSP_CLK_FREQ_RANGE, but

there are no other constraints on configuring DSPCLK in these circumstances.

If DSPCLK is the Timer clock source, the Timer pauses when DSPCLK stops, and resumes operation when

DSPCLK restarts. If DSPCLK is not the clock source, the Timer operation continues when DSPCLK stops, but the

Timer no longer synchronizes to DSPCLK.

4.16.6 Miscellaneous Clock Controls

The CS47L35 incorporates a 32-kHz clock circuit, which is required for input signal debounce, microphone/accessory

detect, and for the Charge Pump 2 (CP2) circuits. The 32-kHz clock must be configured and enabled whenever any of

these features are in use.

The 32-kHz clock can be generated automatically from SYSCLK, or may be input directly as MCLK1 or MCLK2. The

32-kHz clock source is selected using CLK_32K_SRC. The 32-kHz clock is enabled by setting CLK_32K_ENA.

A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. See Section 4.14 for details on configuring

a GPIO pin for this function.

The CS47L35 provides integrated pull-down resistors on the MCLK1 and MCLK2 pins. This provides a flexible capability

for interfacing with other devices.

The clocking scheme for the CS47L35 is shown in Fig. 4-63.

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