CS47L35 datasheet(58/300 Pages) CIRRUS

58 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the

commanded DRC and digital mixing functions. If the frequency is too low, an attempt to enable a DRC signal path fails.

Note that active signal paths are not affected under such circumstances.

The FX_STS field in register R3585 indicates the status of each of the EQ, DRC, and LHPF signal paths. If an

underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled.

The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error

condition occurs, these bits indicate which mixers have been enabled.

R3722 (0x0E8A)

DRC2_ctrl3

15:12 DRC2_NG_

MINGAIN[3:0]

0000 DRC2 Minimum gain to attenuate audio signals when the Noise Gate is active.

0000 = –36 dB

0001 = –30 dB

0010 = –24 dB

0011 = –18 dB

0100 = –12 dB

0101 = –6 dB

0110 = 0 dB

0111 = 6 dB

1000 = 12 dB

1001 = 18 dB

1010 = 24 dB

1011 = 30 dB

1100 = 36 dB

1101 to 1111 = Reserved

11:10 DRC2_NG_

EXP[1:0]

DRC2 Noise-Gate slope

00 = 1 (no expansion)

01 = 2

10 = 4

11 = 8

9:8 DRC2_QR_

THR[1:0]

DRC2 Quick-release threshold (crest factor in dB)

00 = 12 dB

01 = 18 dB

10 = 24 dB

11 = 30 dB

7:6 DRC2_QR_

DCY[1:0]

DRC2 Quick-release decay rate (seconds/6 dB)

00 = 0.725 ms

01 = 1.45 ms

10 = 5.8 ms

11 = Reserved

5:3 DRC2_HI_

COMP[2:0]

011

DRC2 Compressor slope (upper region)

000 = 1 (no compression)

001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

110–111 = Reserved

2:0 DRC2_LO_

COMP[2:0]

000

DRC2 Compressor slope (lower region)

000 = 1 (no compression)

001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101–11X = Reserved

R3723 (0x0E8B)

DRC2_ctrl4

10:5 DRC2_KNEE_

IP[5:0]

0x00 DRC2 Input signal level at the compressor knee.

0x00 = 0 dB

0x01 = –0.75 dB

0x02 = –1.5 dB

… (–0.75-dB steps)

0x3C = –45 dB

0x3D–-0x3F = Reserved

4:0 DRC2_KNEE_

OP[4:0]

0x00 DRC2 Output signal at the compressor knee.

0x00 = 0 dB

0x01 = –0.75 dB

0x02 = –1.5 dB

… (–0.75 dB steps)

0x1E = –22.5 dB

0x1F = Reserved

R3724 (0x0E8C)

DRC2_ctrl5

9:5 DRC2_

KNEE2_IP[4:0]

0x00 DRC2 Input signal level at the noise-gate threshold Knee 2.

0x00 = –36 dB

0x01 = –37.5 dB

0x02 = –39 dB

… (-1.5-dB steps)

0x1E = –81 dB

0x1F = –82.5 dB

Applicable only if DRC2_NG_ENA = 1.

4:0 DRC2_

KNEE2_

OP[4:0]

0x00 DRC2 Output signal at the noise-gate threshold Knee 2.

0x00 = –30 dB

0x01 = –31.5 dB

0x02 = –33 dB

… (–1.5dB steps)

0x1E = –75 dB

0x1F = –76.5 dB

Applicable only if DRC2_KNEE2_OP_ENA = 1.

Table 4-14. DRC2 Control Registers (Cont.)

Bit

Label

Default

Description

CS47L35 датащи(PDF) 58 Page - Cirrus Logic

CS47L35 датащи(HTML) 58 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL